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Everything posted by zhaolinger

  1. How is DLU capacity usage (for Visilogic) calculated or maybe allocated. It doesn't seem to match up the PLC memory distribution and there is no indication (information) given on what is taking up the DLU capacity. As my project grow, the DLU capacity grow too, but it doesn't seem to free up the DLU capacity even I deleted 20 displays and half the numbers of subroutine from my project while the PLC memory distribution will reduce greatly. Why? Why as I add more display and subroutine the DLU capacity got used up but it did not free up when I remove displays and subroutines even through PLC memory usage get reduced greatly (by 35%). Can Unitronic gurus here enlighten me on this strange phenomenon and give advice on how to free up DLU capacity without creating a new projects (I know this will fix it, but I recycle the same project file for different projects and delete the unneeded stuff after completion). Thanks in advance.
  2. Thanks Damian, you are great! You even get to the length of situation on how a test condition may get superseded and overwritten with a unexpected result even when a condition in with a single nets. This is a great example, I bets many others beside me will too benefited from yours above explanation, when they facing similar situations. Regarding using sub-routine as bookmark, yes, I agree with you on that too, while it doesn't simplify my code, it does help me to find code of different group of purpose more easily. Thanks, you and Joe are really, yours information helps me alot in getting my first PLC project moving in the right direction in the shortest time.
  3. Damian, Thanks for these pointers you have given me, it really helps me a lot, I was able to somehow understand the background concepts of these Unitronics PLCs in the shortest time possible because of yours and Joe’s kind pointers given to me these few days. The STL View tips is really useful, it actually convert and display the net in Boolean algebra format once you understand how to read those symbols, and that is where our fundamental of digital logic shine. We can actually spot a logical error using STL view (logical errors are always a headache to any programmers). From these information you provide above, it seem that Unitronics PLCs inherent much of the properties of a microcontroller. The evaluating of normal coils is just bit operation of the Boolean equations displayed by the STL view each time a net is scanned. Hence, it wasn't the ladder condition that is evaluated, instead it is the Boolean equation of that net got evaluated (as a result, one may need to set some operation critical memory bit to initial reset state to ensure it don't got initialized with a on state at power-up). For a latched coil, because the value must be practically latched (actually all memory bits are latched until you power off), so the set and reset coil shall only be executed when the conditions hold true, hence a Boolean equation cannot be used, instead, the ladder condition is evaluated to a register memory and then a compare and jump conditions is checked to determine whether to set/reset the target memory bit or just do nothing and go to the next net. For Timer coils (pulse), most likely it is making use of the timer interrupts of microcontroller to do the countdown, and for TD timer, a check condition is done at every scan and reset the timer call if its ladder conditions no longer hold true. (Hence I presume the timer output is also latched by default unless it is designed to reset it on the next scan). The sub-routine call also behave the same way as that of a microcontroller, call in with no data feed allowed (unlike the case of any software language/VHDL), do operations and change data in memory address and return to the calling address without returning any value directly;the sub-routine in VisiLogic just behave the same way, any coil changed by the sub-routine will have its value latched (thanks Joe answering me this part in my other post) until another ladder access and change it. Since PLCs is not actually a hardware connections of real contacts and coils in series/parallel, the net that got executed latter will always supersede the one that got executed before it, so if the conditions ladder that change the same memory bit are not mutually exclusive, one might get logical error in his program and it will be very hard to seek out the root of problem. A good way to avoid this is to put all conditions that change the same coil into a single net so that the Boolean equation is evaluated as a single equation. With this, the use of sub-routine in PLCs seem kind of redundant now to me. In the case of microcontroller, a sub-routine is to call and reuse a commonly repetitive task so as to shorten the code to be more manageable and easier to read, But for a PLCs, the whole main module is already nested in a huge never ending while loop, so the use of sub-routine no longer so meaningful in a PLCs program, because the whole of main module already repetitive in nature. But by executing a sub-routine only through conditions in a PLC program, it does shorten the time needed to scan through 1 single cycle (saving the CPU cycles wasted on executing a sub-routine that is not needed), if the PLC program is getting real huge and lots of timer interrupts are used, this advantage might become a critical requirement. Hence I also presume most other functional blocks would pretty much behave the same way a microcontroller would, but I haven't explore into these functional block yet. And again, thanks for helping me understand how a PLC works.
  4. I have a idea of making use of sub-routines to model a state machine since the sub-routines can be make to only be called when its inputs ladders condition is true. But to do that, I need to fully understand how a relay that got energized within a sub-routine will behave after the calling of that sub-routine is isolated. To further explain my question, I will create a scenarios of a simple ladder program here. Let say we have Input 1, Sub-routine "Sub1", Relay 1, Timer (Delay) 1, Output 1. See the attached picture for the ladder connections. Main Module Sub-routine 1 My first question is can I assume that both the Timer 1 and Output 1 will not be active until Input 1 is on, because Sub1 won't be scanned until Input 1 energized Relay 1. Correct me if I'm wrong here. Next, after the sub-routine Sub1 become active, Timer 1 will be activated and start countdown, Output 1 will be energized. After Timer 1 finished its countdown, it will cut-off the source of Relay 1 (de-energize) and isolate Sub1 from being call the next scan onward. So, my next question is after that will Output 1 remain energized (because its inputs condition still hold true), or be de-energized (because the sub-routine that energize it no longer be called). Experts over here, please enlighten me on this, because there is no software mode simulation in VisiLogic to prove whether my thought is feasible.
  5. To Damian, Thanks you so much for your kind inputs on my questions, your post actually highlighted the situation I am facing right now. Actually I am quite new to the world of PLCs, it is considered my very first project on PLCs with no experience before, I got quite a bit of experiences in VHDL, but PLCs seem to play a different rules. From what you saying, Visilogic will always execute a normal coil at each scans even the preceding ladder conditions hold false (energize it if true, and de-energize it if false), while a Latched Coil will only be executed with ladder conditions hold true. From what you said that Visilogic will go back an re-execute your "test" operations for the branches, does it means that a badly timed (staged) stages machine model will go hype-wire if Visilogic re-execute a branch (net) when another branch reference to the same MB, and hence the result may evaluate differently if the ladder conditions of that branch had changed. Thanks for the warning, I will be-careful on this part. And the part regarding the STL view you mentioned, any references on what those symbols mean? Let me make some guesses, correct me if I'm wrong. 1. ! is NOT 2. = is Coil Output 3. & is Logical AND 4. &N is AND NOT 5. / is Logical OR And what about LB0, I never declared it in my ladder program, yet the STL show it on the Net STL view, so can you tell me what is it? What purpose it serve? What behaviour it have? Sorry if these questions sound like newbie, I was a newbie in this field and I really appreciate yours kinds inputs on these questions.
  6. Thanks for clarifying my doubt, when I first see a Unitronics PLC sources written with multiple coils connected in series, my thought is “What? I remember I read it on book that this is not allowed.” While VisiLogic don’t allow software mode simulation, there is no way I can see how such connections will behave. Without understand this part, it’s hard for me to understand the original intention of the program. You clarification in this really save me my day. So from what you are saying, if 2 Timers connected in series, they both will be activated (start its countdown) at the same time when the contacts conditions hold true, right? Another doubt I like to clarify, for Timer unit in Unitronics PLCs, they are positive clock edge activated or contact activated (the input must stay charged until the timer finished counting).? Thanks you for your help.
  7. Let say coil A and coil B are connected in series, can I say that coil B will be active when coil A is active. So, for a normal coil/relay, they are no different from coil A and coil B connected in parallel to whatever conditional combinations connected to coil A, isn't it? But for the case of Timer coils (or sub-routines or counters), if Timer A and Timer B connected in series, does it mean that Timer B only start counting after Timer A is active, in short, means the output of Timer A is connected as a NO contact to input of Timer B, am I right to say that? And so for the case of sub-routines, the procedures of the different sub-routines that connected in series will be executed sequentially as compare to the arrangement of nets numbers which will still have all the nets be executed concurrently. Were my assumptions correct? Please, can any expert here enlighten me on these doubts? Thanks in advance.
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