Damian,
Thanks for these pointers you have given me, it really helps me a lot, I was able to somehow understand the background concepts of these Unitronics PLCs in the shortest time possible because of yours and Joe’s kind pointers given to me these few days.
The STL View tips is really useful, it actually convert and display the net in Boolean algebra format once you understand how to read those symbols, and that is where our fundamental of digital logic shine. We can actually spot a logical error using STL view (logical errors are always a headache to any programmers).
From these information you provide above, it seem that Unitronics PLCs inherent much of the properties of a microcontroller.
The evaluating of normal coils is just bit operation of the Boolean equations displayed by the STL view each time a net is scanned. Hence, it wasn't the ladder condition that is evaluated, instead it is the Boolean equation of that net got evaluated (as a result, one may need to set some operation critical memory bit to initial reset state to ensure it don't got initialized with a on state at power-up).
For a latched coil, because the value must be practically latched (actually all memory bits are latched until you power off), so the set and reset coil shall only be executed when the conditions hold true, hence a Boolean equation cannot be used, instead, the ladder condition is evaluated to a register memory and then a compare and jump conditions is checked to determine whether to set/reset the target memory bit or just do nothing and go to the next net.
For Timer coils (pulse), most likely it is making use of the timer interrupts of microcontroller to do the countdown, and for TD timer, a check condition is done at every scan and reset the timer call if its ladder conditions no longer hold true. (Hence I presume the timer output is also latched by default unless it is designed to reset it on the next scan).
The sub-routine call also behave the same way as that of a microcontroller, call in with no data feed allowed (unlike the case of any software language/VHDL), do operations and change data in memory address and return to the calling address without returning any value directly;the sub-routine in VisiLogic just behave the same way, any coil changed by the sub-routine will have its value latched (thanks Joe answering me this part in my other post) until another ladder access and change it.
Since PLCs is not actually a hardware connections of real contacts and coils in series/parallel, the net that got executed latter will always supersede the one that got executed before it, so if the conditions ladder that change the same memory bit are not mutually exclusive, one might get logical error in his program and it will be very hard to seek out the root of problem. A good way to avoid this is to put all conditions that change the same coil into a single net so that the Boolean equation is evaluated as a single equation.
With this, the use of sub-routine in PLCs seem kind of redundant now to me. In the case of microcontroller, a sub-routine is to call and reuse a commonly repetitive task so as to shorten the code to be more manageable and easier to read, But for a PLCs, the whole main module is already nested in a huge never ending while loop, so the use of sub-routine no longer so meaningful in a PLCs program, because the whole of main module already repetitive in nature. But by executing a sub-routine only through conditions in a PLC program, it does shorten the time needed to scan through 1 single cycle (saving the CPU cycles wasted on executing a sub-routine that is not needed), if the PLC program is getting real huge and lots of timer interrupts are used, this advantage might become a critical requirement.
Hence I also presume most other functional blocks would pretty much behave the same way a microcontroller would, but I haven't explore into these functional block yet.
And again, thanks for helping me understand how a PLC works.