PLC Idle stop ?

[micapp]

I have a 570 with some hickup. Sometimes it stops: Status Stop - Idle with Fatal error, Ldr #68. The desription varies.I have tried to make a watchdog with a circuit that restart the PLC when this error occur, but have not suceeded. I try to use an output that when it falls the restart ciruit is ativated, but the output will not fall when the error occur. Is there an SB that is set or reset when this type of error occur? Or do anyone have a solution on the original problem?

 

[Joe Tauser]

The Ldr error is caused by something in your ladder program gone wrong, but I don't know how to extract the exact location from the #68 pointer.  This is a question for the Creators.

 

Post your code and maybe one of use can see the problem.

 

Joe T.

[micapp]

_Jarnes.vlp

 

_{It is written in Norwegian, can you help anyway?}

[Joe Tauser]

For starters you're calling a subroutine from the Main in network 9 that utilizes SMS_5 before you config SMS_5 in network 12.  It doesn't matter that you have check bits in front if it - the fact that it's there means it will be compiled and solved in that order.

 

Your code needs to be organized - you've got inits and configs all over the place.  

 

Put them all in the beginning of the Main subroutine before you call anything else.

 

Also - in network 53 and a couple other places you're driving an INC block with SB 3, which the Creators chose to label "1 second pulse".  It is not.  It is a one second squarewave with a 50% duty cycle, which will drive your INC block crazy.  Use SB 13 - Rising Edge of 1 second pulse.

 

Same for SB 7 - use SB 15 instead.

 

Joe T.

[micapp]

Thanks!

I learned a lot here! Will try this and report back

[Cara Bereck Levy]

Joe T, I saw this while I was editing something in the VisiLogic Help file, so I added your explanation of SB 3, and requested it be added to the SB description.

Thanks--definitely makes it clearer