orisantander Posted December 12, 2018 Report Share Posted December 12, 2018 Hello again! This time I'm wondering if there is a rule to add the IO modules. Is it necessary to configure the digital I/O before the analogue ones? I have this configuration: v1040 + EX-RC1 + (#0: IO-AT8) + (#1: IO-ATC8 )+ (#2: IO-ATC8) + (#3: IO-ATC8) + (#4: IO-AO6X) I need to add an IO-RO16 as module #5 but i have this warning: I'm not sure what can be wrong. If someone could give me an idea please... Thanks in advance! Link to comment Share on other sites More sharing options...
MVP 2023 Ausman Posted December 12, 2018 MVP 2023 Report Share Posted December 12, 2018 I think that you're getting into being over the I/O limit. When you enter your operands into the Hardware config window, there is a "calculator" at the bottom which shows capacity in use and space left. For example, a fully utilised ATC8 uses 16% on an RC1. I didn't run through your setup completely because it would have taken time to do it all. It can be confusing because you actually have to assign everything for the count to be "checkable". If you don't assign everything, it will let you add things over the innate limit and you will think it is ok. This old topic might help: cheers, Aus Link to comment Share on other sites More sharing options...
orisantander Posted December 12, 2018 Author Report Share Posted December 12, 2018 19 minutes ago, Ausman said: I think that you're getting into being over the I/O limit Thanks Ausman, I checked the calculator and it shows 72% with the 6 modules. Is there anything else that could be wrong? Thanks! Link to comment Share on other sites More sharing options...
MVP 2023 Ausman Posted December 12, 2018 MVP 2023 Report Share Posted December 12, 2018 72% doesn't make sense, have you assigned everything? But I agree, it looks like you are under. In theory it is (16% x 4) + 12% = 76% Perhaps you've already got incorrectly assigned I/Os that you've missed somewhere, that the compiler is picking up? Joe T will likely have more wisdom on this. cheers, Aus Link to comment Share on other sites More sharing options...
orisantander Posted December 13, 2018 Author Report Share Posted December 13, 2018 1 hour ago, Ausman said: Perhaps you've already got incorrectly assigned I/Os that you've missed somewhere, that the compiler is picking up? I'm trying to figure it out. I've been following the examples of communications but I can't see what could be the problem. Here are my codes, I know it take time to take a look but I would appreciate all the help! Thanks a lot! P796 - RO EX-RC1_Hospital.vlp P796 - RO PLC for EX-RC1_Hospital.vlp Link to comment Share on other sites More sharing options...
sgull Posted December 13, 2018 Report Share Posted December 13, 2018 (edited) I think the position you put the RO16 will determine what I/O registers are expected in the PLC. The PLC looks at the modules as if they were directly connected. In the EX-RC1, if you are mapping the outputs to a different address to the expected the PLC will see this as being incorrect. The outputs should still work but you will keep getting this error on compile. See Attached regards Denis IO-RO16-IO-RO16L_540802102.pdf Edited December 13, 2018 by sgull Attached file Link to comment Share on other sites More sharing options...
orisantander Posted December 13, 2018 Author Report Share Posted December 13, 2018 6 hours ago, sgull said: In the EX-RC1, if you are mapping the outputs to a different address to the expected the PLC will see this as being incorrect. The outputs should still work but you will keep getting this error on compile. Denis, Thanks for this information. As RO16 is module #6, the outputs start at O112 in the EX-RC1 and on the PLC I'm mapping to the same addresses. However, I'm gonna test it on field and see if it still work! Another thing I just see is my UniCan Send block config on the PLC. I'm not sure if I'm setting the correct parameters. This is what I have: I had the Lenght parameter set on 7 and I just changed to 16, haven't tested on field but still have the same hardware warning. Thanks for all your help! Link to comment Share on other sites More sharing options...
MVP 2023 Ausman Posted December 13, 2018 MVP 2023 Report Share Posted December 13, 2018 Haven't had a chance to look at your program in depth. Unican can get very confusing when specifying Vectors involved in any structs. Visilogic doesn't really help at all with the way it names things, and I have touched on this in the past. Whenever I construct a more complex series of Structs, I lay it all out in an excel sheet, with it clearly in front of me what goes where. Any vector in use, I label the entire block of all the MIs involved in a way I can easily identify, eg MI1000 = VectStr1OUT-0, MI1001 = VectStr1OUT-1, etc. .......and MI1100 = VectStr1IN-0 etc. I do this even if I'm not using all the 16 MIs, thus keeping the space free for possible future use. This way you ensure that you never accidentally use an MI that is involved in a vector, because it appears free but is is actually in use in a "hidden" way. I also use a time based trigger to activate the unican send. But you can't make it too small.....I have had issues with wanting to do things too fast, most of the time SB13 is easy and good enough. cheers, Aus Link to comment Share on other sites More sharing options...
sgull Posted December 13, 2018 Report Share Posted December 13, 2018 Hi What addresses is the PLC saying are not supported? Is it O112 to OO127 or some other range? Link to comment Share on other sites More sharing options...
orisantander Posted December 19, 2018 Author Report Share Posted December 19, 2018 Hello! I'm updating this post! After a couple os tests on field, it's working. I still have the same warnings on compile but it works. On 12/13/2018 at 2:31 AM, sgull said: The outputs should still work but you will keep getting this error on compile. Thanks a lot for your kind help! Cheers! Link to comment Share on other sites More sharing options...
MVP 2023 Ausman Posted December 19, 2018 MVP 2023 Report Share Posted December 19, 2018 Thanks for the feedback, all good to know. cheers, Aus Link to comment Share on other sites More sharing options...
MVP 2023 Joe Tauser Posted December 20, 2018 MVP 2023 Report Share Posted December 20, 2018 I'm a little late to the party, but I downloaded the program you posted on 12/12/18 and didn't get any compile errors. What version of Visilogic are you using? I'd be interested in seeing your latest, program, too. Joe T. Link to comment Share on other sites More sharing options...
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